1. Field of the Invention
The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET) and a method of fabricating the same. More specifically, the present invention relates to a MOSFET having a recessed channel, which is suitable for highly integrated semiconductor circuits, and a method of fabricating the same.
2. Description of the Related Art
As MOSFETs become highly integrated, their channel length decreases and they become more adversely affected by short channel effect and source/drain punch-through. To overcome the reduction in the channel length due to the device shrinkage, a MOSFET having a recessed channel is proposed. This recessed trench is formed in a region that is to be used as the channel of a transistor and it aids in effectively increasing the channel length. Thus, the area of a device can be further scaled down.
As shown in FIG. 1, a conventional MOSFET having a recessed channel comprises a recessed trench 30 formed in a silicon substrate 10, which is bonded to a gate electrode 60 formed on the silicon substrate 10. Here, the critical dimension (CD) L1 of the recessed trench 30 is adjusted to be less than the CD L2 of the gate electrode 60 such that the gate electrode 60 outwardly overlaps the entire recessed trench 30. Thus, during the patterning required to shape the gate electrodes there is a small misalignment margin of error when attempting to form the gate electrodes over the trenches.
However, in this structure, due to a patterning limit, it is difficult to form the recessed trench 30 having a small CD by using photolithography. Thus, a complicated process is required comprising patterning a silicon nitride mask for defining an opening on a substrate, forming spacers on sidewalls of the silicon nitride mask to reduce the CD of the opening, and etching the substrate disposed under the opening. Also, an electric field, which is focused on upper edges 70 of the recessed trench 30, allows a leakage current to increase. In FIG. 1, reference numeral 15 denotes a device isolation layer, 35 denotes a gate oxide layer, 50 denotes a gate conductive layer, 55 denotes a capping layer, and 65 denotes a spacer.